Semiconductor chips are fabricated on suitable flat substrate wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon wafers, etc. After making the active devices, a series of steps are performed to connect the various devices with highly conducting wiring structures, so they can have communication with each other to perform logic or memory storage operations. These wiring structures or interconnect structures are essentially a skeletal network of conducting materials, typically metals, in a matrix of dielectric materials. In high performance devices and to improve device density and yield, it may be desirable to minimize topographic features within the interconnect layers for any given device and across the entire substrate. One common method of forming these high performance interconnect layers is the damascene process.
Multiple types of damascene structures are known, however single and dual damascene processes are the most common. In single damascene, each metal or via layer is fabricated in a series of operations, while in dual damascene, a metal layer and a via layer may be fabricated in a similar operation. Of these two, the dual damascene technique may be preferred because of lower cost and higher device performance.
In the single damascene process, a suitable substrate with or without devices is coated with a suitable resist layer. The resist layer is imaged to define desirable patterns by lithographic methods on the substrate. Cavities are etched on the patterned substrates typically by reactive ion etching (RIE) methods. The etched cavities are cleaned to remove RIE residues. The patterned substrate is then coated with a suitable barrier/seed layer prior to overfilling the cavities with a suitable metal, typically copper, by electro-deposition from a superfilling plating bath chemistry.
The damascene process may be repeated to form multiple layers of interconnects, and the top surface of the substrate is polished. As a result of the discontinuity in the properties (difference in mechanical properties, polishing rates, etc.) of the metal and insulator, and their respective interactions with the polishing pad, polishing slurry, and other process parameters, the polishing produces erosion in high metal pattern density features and dishing in large metal structures. The higher the metal pattern density, the higher the erosion in the dielectric layer. Similarly, the larger the size of the metal cavity, the worse the gravity of the dishing defect. These deleterious defects can cause a variety of defects in subsequent layers, reducing device yield.
Similar results are observed in cross section topographic profiles of polished through silicon via (TSV) structures. The centers of the vias are typically lower than the surface of the insulators.
Among the consequences of dishing on the interconnect structures is poor flatness of the conductor and much higher temperatures typically needed to bond devices to the dished substrate or for wafer to wafer bonding using so called hybrid bonding, i.e. DBI® techniques. With very large pads, dishing can be too deep for the opposing device's surfaces to mate intimately and to form a grain contact or inter-diffusion bond, as the metal may not expand enough at annealing temperatures to form the diffusion bond. Also, the poor flatness on the conductor surface often produces defective bonds, when the surface is bonded or attached to other devices or substrates.
Attempts to reduce the impact of these defects have included the incorporation of dummy dielectric features within large copper structures in dual damascene features for chip interconnects. This can effectively reduce the dishing in copper pads, since the metal width is significantly reduced as compared to previous large pads without dummy dielectric features within them. This approach has been helpful, but it has also increased mask design complexity and the associated loss of freedom of structure placement on the modified pads.